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<h1 class="heading">tru_wishbone_slave</h1>
<h3>Topology Resolution Unit (TRU)</h3>
<p></p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">TRU Global Control Register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">TRU Global Status Register 0</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">TRU Global Status Register 1</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Pattern Control Register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Link Aggregation Control Register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Transition Control General Register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Transition Control PAUSE/Block Register</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Transition Control Port Register</a></span><br/>
<span style="margin-left: 20px; ">3.9. <A href="#sect_3_9">Transition Status Register</a></span><br/>
<span style="margin-left: 20px; ">3.10. <A href="#sect_3_10">Real Time Reconfiguration Control Register</a></span><br/>
<span style="margin-left: 20px; ">3.11. <A href="#sect_3_11">HW-frame gen/det config</a></span><br/>
<span style="margin-left: 20px; ">3.12. <A href="#sect_3_12">TRU Table Register 0</a></span><br/>
<span style="margin-left: 20px; ">3.13. <A href="#sect_3_13">TRU Table Register 1</a></span><br/>
<span style="margin-left: 20px; ">3.14. <A href="#sect_3_14">TRU Table Register 2</a></span><br/>
<span style="margin-left: 20px; ">3.15. <A href="#sect_3_15">TRU Table Register 3</a></span><br/>
<span style="margin-left: 20px; ">3.16. <A href="#sect_3_16">TRU Table Register 4</a></span><br/>
<span style="margin-left: 20px; ">3.17. <A href="#sect_3_17">TRU Table Register 5</a></span><br/>
<span style="margin-left: 20px; ">3.18. <A href="#sect_3_18">Debug port select</a></span><br/>
<span style="margin-left: 20px; ">3.19. <A href="#sect_3_19">Packet Injection Debug Register</a></span><br/>
<span style="margin-left: 20px; ">3.20. <A href="#sect_3_20">Packet Filter Debug Register</a></span><br/>
<span style="margin-left: 20px; ">3.21. <A href="#sect_3_21">RT Reconfig Debug Register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#GCR">TRU Global Control Register</a>
</td>
<td  class="td_code">
tru_gcr
</td>
<td  class="td_code">
GCR
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#GSR0">TRU Global Status Register 0</a>
</td>
<td  class="td_code">
tru_gsr0
</td>
<td  class="td_code">
GSR0
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#GSR1">TRU Global Status Register 1</a>
</td>
<td  class="td_code">
tru_gsr1
</td>
<td  class="td_code">
GSR1
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#MCR">Pattern Control Register</a>
</td>
<td  class="td_code">
tru_mcr
</td>
<td  class="td_code">
MCR
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#LACR">Link Aggregation Control Register</a>
</td>
<td  class="td_code">
tru_lacr
</td>
<td  class="td_code">
LACR
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#TCGR">Transition Control General Register</a>
</td>
<td  class="td_code">
tru_tcgr
</td>
<td  class="td_code">
TCGR
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#TCPBR">Transition Control PAUSE/Block Register</a>
</td>
<td  class="td_code">
tru_tcpbr
</td>
<td  class="td_code">
TCPBR
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#TCPR">Transition Control Port Register</a>
</td>
<td  class="td_code">
tru_tcpr
</td>
<td  class="td_code">
TCPR
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#TSR">Transition Status Register</a>
</td>
<td  class="td_code">
tru_tsr
</td>
<td  class="td_code">
TSR
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x9
</td>
<td >
REG
</td>
<td >
<A href="#RTRCR">Real Time Reconfiguration Control Register</a>
</td>
<td  class="td_code">
tru_rtrcr
</td>
<td  class="td_code">
RTRCR
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xa
</td>
<td >
REG
</td>
<td >
<A href="#HWFC">HW-frame gen/det config</a>
</td>
<td  class="td_code">
tru_hwfc
</td>
<td  class="td_code">
HWFC
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xb
</td>
<td >
REG
</td>
<td >
<A href="#TTR0">TRU Table Register 0</a>
</td>
<td  class="td_code">
tru_ttr0
</td>
<td  class="td_code">
TTR0
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xc
</td>
<td >
REG
</td>
<td >
<A href="#TTR1">TRU Table Register 1</a>
</td>
<td  class="td_code">
tru_ttr1
</td>
<td  class="td_code">
TTR1
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xd
</td>
<td >
REG
</td>
<td >
<A href="#TTR2">TRU Table Register 2</a>
</td>
<td  class="td_code">
tru_ttr2
</td>
<td  class="td_code">
TTR2
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0xe
</td>
<td >
REG
</td>
<td >
<A href="#TTR3">TRU Table Register 3</a>
</td>
<td  class="td_code">
tru_ttr3
</td>
<td  class="td_code">
TTR3
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0xf
</td>
<td >
REG
</td>
<td >
<A href="#TTR4">TRU Table Register 4</a>
</td>
<td  class="td_code">
tru_ttr4
</td>
<td  class="td_code">
TTR4
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x10
</td>
<td >
REG
</td>
<td >
<A href="#TTR5">TRU Table Register 5</a>
</td>
<td  class="td_code">
tru_ttr5
</td>
<td  class="td_code">
TTR5
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x11
</td>
<td >
REG
</td>
<td >
<A href="#DPS">Debug port select</a>
</td>
<td  class="td_code">
tru_dps
</td>
<td  class="td_code">
DPS
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x12
</td>
<td >
REG
</td>
<td >
<A href="#PIDR">Packet Injection Debug Register</a>
</td>
<td  class="td_code">
tru_pidr
</td>
<td  class="td_code">
PIDR
</td>
</tr>
<tr class="tr_even">
<td  class="td_code">
0x13
</td>
<td >
REG
</td>
<td >
<A href="#PFDR">Packet Filter Debug Register</a>
</td>
<td  class="td_code">
tru_pfdr
</td>
<td  class="td_code">
PFDR
</td>
</tr>
<tr class="tr_odd">
<td  class="td_code">
0x14
</td>
<td >
REG
</td>
<td >
<A href="#PTRDR">RT Reconfig Debug Register</a>
</td>
<td  class="td_code">
tru_ptrdr
</td>
<td  class="td_code">
PTRDR
</td>
</tr>
</table>

<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
rst_n_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Global Control Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_clk_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gcr_g_ena_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_addr_i[4:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gcr_tru_bank_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_data_i[31:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gcr_rx_frame_reset_o[23:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&lArr;
</td>
<td  class="td_pblock_left">
wb_data_o[31:0]
</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_cyc_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Global Status Register 0:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rArr;
</td>
<td  class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gsr0_stat_bank_i
</td>
<td  class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_stb_i
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gsr0_stat_stb_up_i[23:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">
&rarr;
</td>
<td  class="td_pblock_left">
wb_we_i
</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">
&larr;
</td>
<td  class="td_pblock_left">
wb_ack_o
</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Global Status Register 1:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_gsr1_stat_up_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Pattern Control Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_mcr_pattern_mode_rep_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_mcr_pattern_mode_add_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_mcr_pattern_mode_sub_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Link Aggregation Control Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_lacr_agg_df_hp_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_lacr_agg_df_br_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_lacr_agg_df_un_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Transition Control General Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_ena_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_clear_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_mode_o[2:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_rx_id_o[2:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_prio_o[2:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcgr_trans_prio_mode_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Transition Control PAUSE/Block Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpbr_trans_pause_time_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpbr_trans_block_time_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Transition Control Port Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpr_trans_port_a_id_o[5:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpr_trans_port_a_valid_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpr_trans_port_b_id_o[5:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tcpr_trans_port_b_valid_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Transition Status Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tsr_trans_stat_active_i
</td>
<td  class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_tsr_trans_stat_finished_i
</td>
<td  class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Real Time Reconfiguration Control Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_rtrcr_rtr_ena_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_rtrcr_rtr_reset_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_rtrcr_rtr_mode_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_rtrcr_rtr_rx_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_rtrcr_rtr_tx_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>HW-frame gen/det config:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_rx_fwd_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_rx_blk_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_tx_fwd_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_tx_blk_id_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_tx_fwd_ub_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_hwfc_tx_blk_ub_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 0:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr0_fid_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr0_sub_fid_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr0_update_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr0_mask_valid_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr0_patrn_mode_o[3:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 1:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr1_ports_ingress_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 2:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr2_ports_egress_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 3:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr3_ports_mask_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 4:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr4_patrn_match_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>TRU Table Register 5:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ttr5_patrn_mask_o[31:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Debug port select:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_dps_pid_o[7:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Packet Injection Debug Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pidr_inject_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pidr_psel_o[2:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pidr_uval_o[15:0]
</td>
<td  class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pidr_iready_i
</td>
<td  class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>Packet Filter Debug Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pfdr_clr_o
</td>
<td  class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pfdr_class_i[7:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_pfdr_cnt_i[15:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">
&nbsp;
</td>
<td  class="td_pblock_right">

</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
<b>RT Reconfig Debug Register:</b>
</td>
<td  class="td_arrow_right">

</td>
</tr>
<tr>
<td  class="td_arrow_left">

</td>
<td  class="td_pblock_left">

</td>
<td  class="td_sym_center">

</td>
<td  class="td_pblock_right">
tru_ptrdr_ging_mask_i[31:0]
</td>
<td  class="td_arrow_right">
&lArr;
</td>
</tr>
</table>

<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="GCR"></a>
<h3><a name="sect_3_1">3.1. TRU Global Control Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_gcr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
GCR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x0
</td>
</tr>
</table>
<p>
Control register containing global (port-independent) settings of the TRU.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_FRAME_RESET[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_FRAME_RESET[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
RX_FRAME_RESET[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRU_BANK
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
G_ENA
</td>
</tr>
</table>
<ul>
<li><b>
G_ENA
</b>[<i>read/write</i>]: TRU Global Enable
<br>Global TRU enable bit. Overrides all port settings.<br>				  0: RTU is disabled. All packets are dropped.<br>				  1: RTU is enabled.
<li><b>
TRU_BANK
</b>[<i>write-only</i>]: Swap TRU TAB bank
<br>write 1: swaps the active bank of the VLAN TAB (writing to TRU TAB affects<br>				  inactive bank, only swapping the banks causes the written data to be activated<br>				  write 0: no effect
<li><b>
RX_FRAME_RESET
</b>[<i>read/write</i>]: Rx Frame Reset
<br>Resets information about filtered frames received on<br>				 a port
</ul>
<a name="GSR0"></a>
<h3><a name="sect_3_2">3.2. TRU Global Status Register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_gsr0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
GSR0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x4
</td>
</tr>
</table>
<p>
Provides status of TRU actions
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_STB_UP[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_STB_UP[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_STB_UP[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
STAT_BANK
</td>
</tr>
</table>
<ul>
<li><b>
STAT_BANK
</b>[<i>read-only</i>]: Active Bank
<br>Indicates active bank in the TRU TAB
<li><b>
STAT_STB_UP
</b>[<i>read-only</i>]: Stable Ports UP
<br>Indicates stable ports which are up (0=down, 1=up)
</ul>
<a name="GSR1"></a>
<h3><a name="sect_3_3">3.3. TRU Global Status Register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_gsr1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
GSR1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x8
</td>
</tr>
</table>
<p>
Provides status of TRU actions
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_UP[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_UP[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_UP[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
STAT_UP[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
STAT_UP
</b>[<i>read-only</i>]: Ports UP
<br>Indicates ports which are up (0=down, 1=up)
</ul>
<a name="MCR"></a>
<h3><a name="sect_3_4">3.4. Pattern Control Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_mcr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
MCR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0xc
</td>
</tr>
</table>
<p>
Defines matching pattern mode/configuration for quick port reconfiguration
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
PATTERN_MODE_SUB[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
PATTERN_MODE_ADD[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
PATTERN_MODE_REP[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PATTERN_MODE_REP
</b>[<i>read/write</i>]: Replace Pattern Mode
<br>Selected Pattern Mode for port config replacement
<li><b>
PATTERN_MODE_ADD
</b>[<i>read/write</i>]: Addition Pattern Mode
<br>Selected Pattern Mode for port config addition
<li><b>
PATTERN_MODE_SUB
</b>[<i>read/write</i>]: Substraction Pattern Mode
<br>Selected Pattern Mode for port config substraction
</ul>
<a name="LACR"></a>
<h3><a name="sect_3_5">3.5. Link Aggregation Control Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_lacr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
LACR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x10
</td>
</tr>
</table>
<p>
Enables configuration of Link Aggregation distribution functions for each kind of traffic.<br>       Available functions:<br>       0: based on pclass detected by Packet Filter (need proper pFilter config)<br>       1: based on destination MAC address (bits 6 and 7)<br>       2: based on source MAC address (bits 6 and 7)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
AGG_DF_UN_ID[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
AGG_DF_BR_ID[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
AGG_DF_HP_ID[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
AGG_DF_HP_ID
</b>[<i>read/write</i>]: HP traffic Distribution Function ID
<br>ID of Aggregation Distribution Function for HP traffic (value of 0 recommended, requires proper pFilter config)
<li><b>
AGG_DF_BR_ID
</b>[<i>read/write</i>]: Broadcast Distribution Function ID
<br>ID of Aggregation Distribution Function for broadcast traffic (value of 2 recommended)
<li><b>
AGG_DF_UN_ID
</b>[<i>read/write</i>]: Unicast Distribution Function ID
<br>ID of Aggregation Distribution Function for unicast traffic
</ul>
<a name="TCGR"></a>
<h3><a name="sect_3_6">3.6. Transition Control General Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_tcgr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TCGR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x14
</td>
</tr>
</table>
<p>
Defines transition mode/configuration for slow port reconfiguration - decides<br>      when two swap banks such that HP packets are not lost.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_PRIO_MODE
</td>
<td style="border: solid 1px black;" colspan=3  class="td_field">
TRANS_PRIO[2:0]
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=3  class="td_field">
TRANS_RX_ID[2:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=3  class="td_field">
TRANS_MODE[2:0]
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_CLEAR
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_ENA
</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
TRANS_ENA
</b>[<i>read/write</i>]: Transition Enabled
<br>Enables/disables transition
<li><b>
TRANS_CLEAR
</b>[<i>read/write</i>]: Transition Clear
<br>Writing 1 clears >Transition Finished< bit so that new transition can be <br>         performed. No new transition will be started until  >Transition Finished< is cleared
<li><b>
TRANS_MODE
</b>[<i>read/write</i>]: Transition Mode
<br>Selected Transitin Mode for port re-config 
<li><b>
TRANS_RX_ID
</b>[<i>read/write</i>]: Rx Detected Frame ID
<br>Base transition on detection of the frame which is parsed into provided CLASS ID
<li><b>
TRANS_PRIO
</b>[<i>read/write</i>]: Priority
<br>Indicates at which traffic priority the transition attempts not to loose <br>         frames
<li><b>
TRANS_PRIO_MODE
</b>[<i>read/write</i>]: Priority Mode
<br>Specifies whether<br>         - 0: use indication of HP packet from RTU (fast match)<br>         - 1: use the priority specified in TRANS_PRIO register<br>         to count packets during transition
</ul>
<a name="TCPBR"></a>
<h3><a name="sect_3_7">3.7. Transition Control PAUSE/Block Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_tcpbr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TCPBR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x18
</td>
</tr>
</table>
<p>
Defines transition mode/configuration for slow port reconfiguration - decides<br>      when two swap banks such that HP packets are not lost.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TRANS_BLOCK_TIME[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TRANS_BLOCK_TIME[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TRANS_PAUSE_TIME[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TRANS_PAUSE_TIME[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
TRANS_PAUSE_TIME
</b>[<i>read/write</i>]: PAUSE Time
<br>Time (quanta) send in hw-generated PAUSE message to the link partner (port B) to block the traffic on configured priority
<li><b>
TRANS_BLOCK_TIME
</b>[<i>read/write</i>]: Output Block Time
<br>Time (quanta) for which output queues of both ports (A and B) are blocked for configured priority
</ul>
<a name="TCPR"></a>
<h3><a name="sect_3_8">3.8. Transition Control Port Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_tcpr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TCPR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x1c
</td>
</tr>
</table>
<p>
Defines transition mode/configuration for slow port reconfiguration - decides<br>      when two swap banks such that HP packets are not lost.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_PORT_B_VALID
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=6  class="td_field">
TRANS_PORT_B_ID[5:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_PORT_A_VALID
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=6  class="td_field">
TRANS_PORT_A_ID[5:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
TRANS_PORT_A_ID
</b>[<i>read/write</i>]: Port A ID
<br>Configuration of port A (PORT ID)
<li><b>
TRANS_PORT_A_VALID
</b>[<i>read/write</i>]: Port A Valid
<br>Configuration of port A (valid bit)
<li><b>
TRANS_PORT_B_ID
</b>[<i>read/write</i>]: Port B ID
<br>Configuration of port B (PORT ID)
<li><b>
TRANS_PORT_B_VALID
</b>[<i>read/write</i>]: Port B Valid
<br>Configuration of port B (valid bit)
</ul>
<a name="TSR"></a>
<h3><a name="sect_3_9">3.9. Transition Status Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_tsr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x20
</td>
</tr>
</table>
<p>
Provides information about the state of transition (if any).
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_STAT_FINISHED
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
TRANS_STAT_ACTIVE
</td>
</tr>
</table>
<ul>
<li><b>
TRANS_STAT_ACTIVE
</b>[<i>read-only</i>]: Transition Active
<br>Indicates that transition is active
<li><b>
TRANS_STAT_FINISHED
</b>[<i>read-only</i>]: Transition Finished
<br>Indicates that transition has been finished
</ul>
<a name="RTRCR"></a>
<h3><a name="sect_3_10">3.10. Real Time Reconfiguration Control Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_rtrcr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x9
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
RTRCR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x24
</td>
</tr>
</table>
<p>
Controls Real Time Handler.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RTR_TX[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RTR_RX[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RTR_MODE[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
RTR_RESET
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
RTR_ENA
</td>
</tr>
</table>
<ul>
<li><b>
RTR_ENA
</b>[<i>read/write</i>]: RTR Enabled
<br>Enables Real Time Reconfiguration Handler
<li><b>
RTR_RESET
</b>[<i>read/write</i>]: RTR Reset
<br>Resets Real Time Reconfiguration Handler
<li><b>
RTR_MODE
</b>[<i>read/write</i>]: RTR Handler Mode
<br>Selected Real Time Reconfig Handler Mode
<li><b>
RTR_RX
</b>[<i>read/write</i>]: RTR Rx Frame ID
<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br>         is programmed to indicate reception of Quick Forward Request BPDUe
<li><b>
RTR_TX
</b>[<i>read/write</i>]: RTR Tx Frame ID
<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br>         (Quick Forward Request BPDUe)
</ul>
<a name="HWFC"></a>
<h3><a name="sect_3_11">3.11. HW-frame gen/det config</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_hwfc
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xa
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
HWFC
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x28
</td>
</tr>
</table>
<p>
Controls HW generation/detection of frames
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_BLK_UB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
TX_FWD_UB[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4  class="td_field">
TX_BLK_ID[3:0]
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
TX_FWD_ID[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RX_BLK_ID[3:0]
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
RX_FWD_ID[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
RX_FWD_ID
</b>[<i>read/write</i>]: HW Frame Rx Forward ID
<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br>         is programmed to indicate reception of Quick Forward Request BPDUe
<li><b>
RX_BLK_ID
</b>[<i>read/write</i>]: HW Frame Rx Block ID
<br> ID (bit number of the rxFrameMask) of the signal from the endpoint which <br>         is programmed to indicate reception of Quick Block Request BPDUe
<li><b>
TX_FWD_ID
</b>[<i>read/write</i>]: HW Frame Tx Forward ID
<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br>         (Quick Forward Request BPDUe)
<li><b>
TX_BLK_ID
</b>[<i>read/write</i>]: HW Frame Tx Block ID
<br> ID (bit number of the txFrameMask) of the HW-sent frame by endpoint<br>         (Quick Block Request BPDUe)
<li><b>
TX_FWD_UB
</b>[<i>read/write</i>]: HW Frame Tx Forward User Byte
<br> LOW byte of the 16-bit User Defined Value inserted into tnjected Template
<li><b>
TX_BLK_UB
</b>[<i>read/write</i>]: HW Frame Tx Block User Byte
<br> LOW byte of the 16-bit User Defined Value inserted into tnjected Template
</ul>
<a name="TTR0"></a>
<h3><a name="sect_3_12">3.12. TRU Table Register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xb
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x2c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4  class="td_field">
PATRN_MODE[3:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
MASK_VALID
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
UPDATE
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
SUB_FID[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
FID[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
FID
</b>[<i>read/write</i>]: Filtering Database ID
<br>Assigns the VID to a particular filtering database
<li><b>
SUB_FID
</b>[<i>read/write</i>]: ID withing Filtering Database Entry
<br>Identifies entry within FID entry
<li><b>
UPDATE
</b>[<i>write-only</i>]: Force TRU table sub-entry update
<br>write 1: flush TTR register to inactive bank of TRU table entry at address <br>         in FID+SUB_FID
<li><b>
MASK_VALID
</b>[<i>read/write</i>]: Entry Valid
<li><b>
PATRN_MODE
</b>[<i>read/write</i>]: Pattern Mode
</ul>
<a name="TTR1"></a>
<h3><a name="sect_3_13">3.13. TRU Table Register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xc
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x30
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_INGRESS[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_INGRESS[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_INGRESS[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_INGRESS[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PORTS_INGRESS
</b>[<i>read/write</i>]: Ingress Mask
</ul>
<a name="TTR2"></a>
<h3><a name="sect_3_14">3.14. TRU Table Register 2</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr2
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xd
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR2
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x34
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_EGRESS[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_EGRESS[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_EGRESS[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_EGRESS[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PORTS_EGRESS
</b>[<i>read/write</i>]: Egress Mask
</ul>
<a name="TTR3"></a>
<h3><a name="sect_3_15">3.15. TRU Table Register 3</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr3
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xe
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR3
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x38
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_MASK[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_MASK[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_MASK[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PORTS_MASK[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PORTS_MASK
</b>[<i>read/write</i>]: Egress Mask
</ul>
<a name="TTR4"></a>
<h3><a name="sect_3_16">3.16. TRU Table Register 4</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr4
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0xf
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR4
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x3c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MATCH[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MATCH[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MATCH[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MATCH[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PATRN_MATCH
</b>[<i>read/write</i>]: Pattern Match
</ul>
<a name="TTR5"></a>
<h3><a name="sect_3_17">3.17. TRU Table Register 5</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ttr5
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x10
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
TTR5
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x40
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MASK[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MASK[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MASK[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PATRN_MASK[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PATRN_MASK
</b>[<i>read/write</i>]: Patern Mask
</ul>
<a name="DPS"></a>
<h3><a name="sect_3_18">3.18. Debug port select</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_dps
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x11
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
DPS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x44
</td>
</tr>
</table>
<p>
Select port number for applying debugging measures in boht: <br>                     Packet Injection Debug Register <br>                     Packet Filter Debug Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
PID[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
PID
</b>[<i>read/write</i>]: Port ID
<br>ID of the port to be debugged
</ul>
<a name="PIDR"></a>
<h3><a name="sect_3_19">3.19. Packet Injection Debug Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_pidr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x12
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
PIDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x48
</td>
</tr>
</table>
<p>
Used for debugging (ctrl/status) HW packet injection of a selected port
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
IREADY
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
UVAL[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
UVAL[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=3  class="td_field">
PSEL[2:0]
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
INJECT
</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
INJECT
</b>[<i>write-only</i>]: Injection Request
<li><b>
PSEL
</b>[<i>read/write</i>]: Packet Select
<br>ID of the packet-template to be sent
<li><b>
UVAL
</b>[<i>read/write</i>]: USER VALUE
<br>Value to be inserted at predefined place in the injected packet
<li><b>
IREADY
</b>[<i>read-only</i>]: Injection Ready
</ul>
<a name="PFDR"></a>
<h3><a name="sect_3_20">3.20. Packet Filter Debug Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_pfdr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x13
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
PFDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x4c
</td>
</tr>
</table>
<p>
This register stores information about detected packages (class, number)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
CNT[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
CNT[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
CLASS[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td  class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1  class="td_field">
CLR
</td>
</tr>
</table>
<ul>
<li><b>
CLR
</b>[<i>write-only</i>]: Clear register
<br>Clears the status regs (count and class)
<li><b>
CLASS
</b>[<i>read-only</i>]: Filtered class
<br>Shows which class messages has been detected
<li><b>
CNT
</b>[<i>read-only</i>]: CNT
<br>Counts all detections (regardless of the class)
</ul>
<a name="PTRDR"></a>
<h3><a name="sect_3_21">3.21. RT Reconfig Debug Register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td  class="td_code">
tru_ptrdr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td  class="td_code">
0x14
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td  class="td_code">
PTRDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td  class="td_code">
0x50
</td>
</tr>
</table>
<p>
This register stores information about detected packages (class, number)
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
31
</td>
<td  class="td_bit">
30
</td>
<td  class="td_bit">
29
</td>
<td  class="td_bit">
28
</td>
<td  class="td_bit">
27
</td>
<td  class="td_bit">
26
</td>
<td  class="td_bit">
25
</td>
<td  class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
GING_MASK[31:24]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
23
</td>
<td  class="td_bit">
22
</td>
<td  class="td_bit">
21
</td>
<td  class="td_bit">
20
</td>
<td  class="td_bit">
19
</td>
<td  class="td_bit">
18
</td>
<td  class="td_bit">
17
</td>
<td  class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
GING_MASK[23:16]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
15
</td>
<td  class="td_bit">
14
</td>
<td  class="td_bit">
13
</td>
<td  class="td_bit">
12
</td>
<td  class="td_bit">
11
</td>
<td  class="td_bit">
10
</td>
<td  class="td_bit">
9
</td>
<td  class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
GING_MASK[15:8]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td  class="td_bit">
7
</td>
<td  class="td_bit">
6
</td>
<td  class="td_bit">
5
</td>
<td  class="td_bit">
4
</td>
<td  class="td_bit">
3
</td>
<td  class="td_bit">
2
</td>
<td  class="td_bit">
1
</td>
<td  class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8  class="td_field">
GING_MASK[7:0]
</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
<td >

</td>
</tr>
</table>
<ul>
<li><b>
GING_MASK
</b>[<i>read-only</i>]: globalIngMask
<br>Global Ingress Mask
</ul>



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